The present invention relates to a method of fabricating a semiconductor device, and particularly to a method of fabricating a highly integrated semiconductor device which includes the steps of forming a contact hole facing a conductive material layer such as a shallow impurity diffusion layer or a metal silicide layer formed on the impurity diffusion layer, and burying the contact hole with a contact plug or an upper layer interconnection, thereby forming a multi-layered interconnection structure having a low contact resistance.
The width of a gate electrode in MIS type transistors is being reduced to be less than a quarter-micron along with the increasing demands toward high integration and high quality of semiconductor devices such as LSIS. In such a fine element structure, in addition to the reduction in the width of a gate electrode, the depth of an impurity diffusion layer is also required to be reduced for lowering a short-channel effect and ensuring a source/drain withstand voltage. For example, for an MIS type transistor having a gate electrode width of 0.25 .mu.m, the depth of an impurity diffusion layer is required to be made shallow to a value less than about 0.08 .mu.m (80 nm).
The tendency to make shallow an impurity diffusion layer, however, increases a sheet resistance of a source/drain region, thereby causing another problem in reducing a response speed and an operation limiting frequency of the semiconductor device. This is because an operation limiting frequency "fth" is inversely proportional to a gate delay time ".tau.pd" (fth.varies.1/.tau.pd) in the MIS type transistor. In particular, such a phenomenon presents a large inconvenience in an MPU (Microprocessing Unit) requiring high speed operation.
To cope with such a problem, a Salicide (Self aligned silicide) process has been proposed, wherein a low resistance metal silicide layer made from TiSi.sub.2, CoSi.sub.2 or the like which is selectively formed on a source/drain region. Now, the Salicide process will be briefly described with reference to FIGS. 5A to 5D.
FIGS. 5A to 5D are schematic sectional views showing a fabrication process of a MOSIC using a common Salicide process. An element isolation region 2 is formed in a semiconducting substrate 1 made from silicon, and a thermal oxide film and a polycrystalline silicon layer are formed on the semiconducting substrate 1, followed by patterning, to form a gate oxide film 3 and a gate electrode 4. Subsequently, ions of an impurity are injected over the entire surface to a shallow depth using the gate electrode 4 as a mask.
An oxide silicon layer is then formed over the entire surface, followed by etching-back over the entire surface, to form side wall spacers 5 on the side surfaces of the gate electrode 4. After that, ions of an impurity are injected again using the gate electrode 4 and the side wall spacers 5 as a mask, followed by activation through heat treatment, to form an impurity diffusion layer 6 having an LDD structure shown in FIG. 5A.
As shown in FIG. 5B, a metal layer 7 made from Ti or the like is formed over the entire surface, and it is subjected to a first heat-treatment at about 600.degree. C. As a result, the metal layer 7 on the impurity diffusion layer 6 is selectively converted into TiSix by solid-phase diffusion. The metal layer 7 does not react with the oxide silicon materials forming the element isolation region 2 and the side wall spacers 5 under the first heat-treatment condition. In the case where the metal layer 7 is formed with the surface of the gate electrode 4 made from polycrystalline silicon exposed, TiSix is also formed on the gate electrode 4. If a spacer made from silicon oxide or the like is formed on the gate electrode 4, TiSix is not formed on the gate electrode 4. The compound TiSix formed by the first heat-treatment has a C49 crystal structure, which has a relatively high resistance.
After that, the non-reactive portion of the metal layer 7 on the element isolation region and the like is removed by wet etching using a mixed solution of ammonia and hydrogen peroxide (NH.sub.3 +H.sub.2 O.sub.2), to selectively leave TiSix on the impurity diffusion layer 6 and the like. The compound TiSix on the impurity diffusion layer 6 and the like is converted into TiSi.sub.2 by a second heat-treatment at about 800.degree. C., to form a self-aligned metal silicide layer 8. Such a state is shown in FIG. 5C. In this figure, the metal silicide layer 8 is shown to be also formed on the gate electrode 4. The compound TiSi.sub.2 formed by the second heat treatment has a C54 crystal structure, which has a resistance (resistivity: about 15 .mu..OMEGA. cm) lower than that of the metal silicide layer having the C49 crystal structure.
The above steps are a main portion of the Salicide process. After that, as shown in FIG. 5D, an interlayer insulating layer 9 is formed in a normal manner and a contact hole 10 facing the impurity diffusion layer 6 is formed in the interlayer insulating film 9. Subsequently, an upper layer interconnection 16 made from Al based metal or W is formed by the so-called metallization step, thus completing a MOSIC (Metal-Oxide-Semiconductor Integrated Circuit).
The MOSIC having the above-described Salicide structure has an advantage that a source/drain resistance thereof is lower than that of a related art MOSIC by about one figure. However, the exposed area of the impurity diffusion layer 6 comes to be finer along with the recent tendency toward finer design rule of the element. If the Salicide process is applied to such a narrow impurity diffusion layer region, the phase-conversion of TiSix from the C49 crystal structure to the C54 crystal structure cannot be smoothly performed. As a result, crystal grains of TiSix having the C49 crystal structure are aggregated during the second heat-treatment at a high temperature, to coarsen the surface of the metal silicide layer, thus making it impossible to reduce a sheet resistance of the metal silicide layer.
The metal silicide layer is also required to be thinned along with the increasing demand to make shallow the impurity diffusion layer. The thinning of the metal silicide layer also acts to accelerate the aggregation of the crystal grains thereof. Accordingly, there is strong demand at present to develop a Salicide process capable of forming a thin metal silicide layer on a narrow impurity diffusion layer region while preventing aggregation of crystal grains of the metal silicide layer and thereby stably obtaining a smooth surface thereof.
The aggregation of crystal grains of a transition metal silicide layer is considered to be due to uneven native oxide inevitably present on the surface of an impurity diffusion layer. The removal of native oxide on the surface of an impurity diffusion layer has been performed by wet processing using a diluted HF solution or sputter etching using Ar.sup.+ of a high ion energy. However, for a highly integrated semiconductor device having a shallow impurity diffusion layer, such a removal process is liable to damage the impurity diffusion layer. In view of the foregoing, the present inventor has proposed a stable Salicide process using a low energy plasma etching system in Japanese Patent Laid-open No. Hei 7-69015, in which native oxide is removed with an incident ion energy being controlled.
The above Salicide process can be stably applied to a highly integrated semiconductor device having a shallow impurity diffusion layer.
A multi-layered interconnection structure is obtained by following steps:
an interlayer insulating film is formed carefully on the metal silicide layer; a contact hole facing the metal silicide layer is formed in the interlayer insulating film; and the contact hole is buried with a contact plug or an upper layer interconnection (metallization). In this case, native oxide is formed again on the surface of the metal silicide layer in a period of time from the steps of forming the contact hole and separating a resist mask to the step of metallization. To obtain a low ohmic contact, it is essential to remove the native oxide formed again on the surface of the metal silicide layer. With native oxide formed on the surface of an impurity diffusion layer, it is usually removed by wet processing using diluted HF solution. However, with the native oxide formed on a metal silicide layer such as TiSi.sub.2 which is exposed at the bottom portion of a contact hole, a desired etching selectively is not obtained, TiSi.sub.2 is etched together with the native oxide. Thus wet processing cannot be used. PA1 forming an interlayer insulating film on a conductive material layer, and forming a contact hole facing the conductive material layer in the interlayer insulating film; PA1 removing native oxide which is formed on the surface of the conductive material layer and exposed at the bottom portion of the contact hole; and PA1 forming either a contact plug or an upper layer interconnection at least in the contact hole; PA1 wherein the native oxide is removed by sputter etching using an incident ion energy having an intensity more than a value allowing the native oxide to be removed by sputter etching and less than a value allowing a side surface of the contact hole to be sputtered and re-deposited on the surface of the conductive material layer exposed at the bottom portion of the contact hole; and PA1 either the contact plug or the upper layer interconnection is formed in the contact hole continuously after removal of the native oxide without exposing, to an oxidizing atmosphere, the surface of the conductive material layer exposed at the bottom portion of the contact hole. PA1 forming an interlayer insulating film on a conductive material layer, and forming a contact hole facing the conductive material layer in the interlayer insulating film; PA1 removing native oxide which is formed on the surface of the conductive material layer and exposed at the bottom portion of the contact hole; and PA1 forming either a contact plug or an upper layer interconnection at least in the contact hole; PA1 wherein the native oxide is removed by sputter etching performed at a substrate temperature more than a value allowing sputter ion species to be entrapped in the conductive material layer exposed at the bottom portion of the contact hole; and PA1 either the contact plug or the upper layer interconnection is formed in the contact hole continuously after removal of the native oxide without exposing, to an oxidizing atmosphere, the surface of the conductive material layer exposed at the bottom portion of the contact hole.
Incidentally, there may be considered a method of removing native oxide by Ar.sup.+ sputter etching using a parallel plate etching system. However, to perfectly remove native oxide on a thin metal silicide layer formed on an impurity diffusion layer by the parallel plate etching system having a low ion intensity, 1,000 eV or more of energy must be imparted to Ar.sup.+. This coarsens the surface of the thin metal silicide layer, and has a large possibility of damaging the shallow impurity diffusion layer. Moreover, when the aspect ratio of the contact hole is as large as 5 or more, the side wall of the contact hole is sputtered by such a strong incident ion energy, and the sputtered component is re-deposited on the bottom portion of the contact hole. Accordingly, the remove of the native oxide does not proceed, failing to reduce a contact resistance. In the above it was described about the semiconductor having the metal silicide layer. Although, the same problem arises in the case where a contact hole facing a shallow impurity diffusion layer is directly formed, followed by metallization.